NXPU

Causal reasoning,in silicon.

NXPU is a hardware reasoning engine that evaluates logic, builds proof trees, and discovers causal structure. Every output is traceable. Nothing is hallucinated. Nothing is guessed.

520 ns
Per Rule
O(N)
vs O(N²) SMT
0
Hallucinations
MIT
Licensed

Language models cannot prove they are right.

They produce text that sounds correct. They cannot show the derivation that led to a conclusion. They cannot distinguish correlation from causation. When wrong, they are wrong confidently.

Medicine, finance, law, defense. These are fields where the reasoning path matters as much as the answer. Where "probably right" is not an acceptable confidence level. Where auditability is a regulatory requirement.

NXPU is fundamentally different: a chip that reasons through logic, not statistics.

Datalog evaluation, in hardware.

NXPU evaluates Datalog, a restricted subset of first-order logic with recursion but guaranteed termination. Rules load, facts assert, and the chip computes all derivable conclusions through semi-naive bottom-up evaluation.

On top: a probabilistic layer. Each derived fact carries a calibrated confidence propagated through the proof tree. The system distinguishes "derived with probability 0.93" from "not derivable." These are fundamentally different statements.

The third layer: causal discovery. The PC algorithm runs in hardware, recovering directed acyclic graphs from observational data. Not pattern matching. Structure learning.

NXPU. Measured on hardware. Not projected.

~520 ns
Per Rule Eval
1.65 uJ
Per Derivation
O(N)
vs O(N²) SMT
F1=0.824
Sachs Benchmark
46/46
Testbenches Pass

Nine subsystems. One NXPU.

Each NXPU module is independently testable with a defined interface contract. The architecture composes: causal results feed probabilistic rules, which feed deterministic chains, with the full proof tree preserved.

01

Deterministic Pipeline

Classical Datalog: unification, join, projection, and recursive fixpoint computation. Rules compile to microcode processed without branching. Semi-naive strategy ensures each fact derived exactly once.

02

Probabilistic Pipeline

Every fact annotated with confidence in [0,1]. Product t-norm for conjunction, probabilistic sum for disjunction. Multiple derivation paths combine correctly. The proof tree records which path contributed what weight.

03

Causal Discovery Unit

PC algorithm with configurable significance thresholds. Conditional independence tests, skeleton construction, and edge orientation via Meek's rules. Output DAGs load directly into the rule engine.

04

Proof Tree Recorder

Not a justification generated after the fact. The derivation path is the computation itself. Every conclusion traceable to its axioms. Every confidence score decomposable into contributing evidence.

Where hallucination is not an option.

Domains where NXPU replaces guesswork with provable, auditable reasoning.

Healthcare

Drug interaction reasoning, clinical decision support with full audit trails, adverse event causal analysis

Finance

Transaction chain analysis, AML compliance checking, fraud causal graphs with regulatory traceability

Legal

Statutory reasoning, precedent chain verification, contract clause entailment with proof export

Cybersecurity

Attack graph reasoning, root-cause analysis from telemetry, automated threat attribution

Defense

Mission planning with provable constraint satisfaction, kill-chain analysis, sensor fusion with provenance

NXPU is fully open source.

The complete NXPU RTL is MIT-licensed. Every SystemVerilog module, every testbench, every rule pack, every synthesis script. Reasoning hardware should be auditable by the people who depend on it.

View on GitHub

NXPU: from dev board to data center.

Dev Board
ZCU104 evaluation kit. Full NXPU bitstream, UART console, example rule packs. For prototyping and integration testing.
1U Appliance
Rack-mount with PCIe host interface, dedicated FPGA, and management plane. For on-premises deployment.
Rack Scale
Multiple NXPU instances with shared fact stores and parallel rule evaluation. Enterprise-scale reasoning workloads.
Cloud API
REST interface to hosted NXPU hardware. Submit rules and facts, receive proof trees. For SaaS integration.
Custom ASIC
Full-custom silicon. 10x clock improvement, 50x energy reduction over FPGA. For volume production.

NXPU platform specs.

Target: Xilinx xczu7ev (ZCU104), 100 MHz

Utilization: 25.4% LUT

Subsystems: 9 independently validated modules

Rule Packs: 24 across 6 reasoning rungs

Validation: 46/46 testbenches, F1=0.824 on Sachs (11-protein causal network)

License: MIT, full RTL at github.com/dyber-pqc/NXPU-public

Build with us.

Research partnerships. Integration pilots. Custom rule packs for your domain.

nxpu@dyber.org